1. Field of the Invention
The present invention relates to a pre-emphasis apparatus and a pre-emphasis method of a low voltage differential signaling (LVDS) transmitter, and more particularly to a pre-emphasis apparatus and a pre-emphasis method of a LVDS transmitter that can perform pre-emphasis using a parallel data signal and a multi-phase clock signal received from an external source.
2. Description of the Related Art
A low voltage differential signaling (LVDS) interface system is a circuit having the characteristics of high-speed operation, low current consumption and low electromagnetic interference (EMI), and generally used in various applications such as a semiconductor device, a liquid crystal display (LCD), a communication system and the like.
It is common for an LVDS interface system to include an LVDS transmitter that transmits a low voltage differential signal and a LVDS receiver that receives the transmitted low voltage differential signal.
FIG. 1 is a block diagram illustrating a configuration of a conventional LVDS transmitter, more particularly of a LVDS transmitter that transmits 8-bit color data of 8-bit in an LCD unit.
Referring to FIG. 1, the conventional LVDS transmitter is composed of a parallel/serial data conversion unit 20, a LVDS driver unit 40, and a phase locked loop (PLL) 30.
A data signal input to the LVDS transmitter is composed of an 8-bit red data signal, an 8-bit green data signal, an 8-bit blue data signal and a 4-bit control data signal. All the input data signals of 28-bit are input in parallel.
The parallel/serial data conversion unit 20 includes four parallel/serial data converters 21, 22, 23 and 24. The parallel/serial data converters 21, 22, 23 and 24 respectively convert input parallel data signals into serial data signals DA, DB, DC and DD in a none-return-to-zero (NRZ) data format.
Here, 7-bit parallel data signals are respectively input to the parallel/serial data converters 21, 22, 23 and 24. That is, since the four parallel data signals of 7-bits are respectively input to the four parallel/serial data converters 21, 22, 23 and 24, a total of 28-bit parallel data signals are input to the four parallel/serial data converters 21, 22, 23 and 24.
The serial data signals DA, DB, DC and DD output from the four parallel/serial data converters 21, 22, 23 and 24 in the parallel/serial data conversion unit 20 are respectively transmitted to four LVDS drivers 41, 42, 43 and 44 in a LVDS driver unit 40. Accordingly, one parallel input data element of 7-bits is serialized and input to each of the LVDS drivers 41, 42, 43 and 44.
The LVDS driver unit 40 converts the input serial data signals DA, DB, DC and DD into LVDS levels to output the converted LVDS level. As shown in FIG. 1, an additional LVDS driver 45 is included in the LVDS driver unit 40 to output a clock signal transmitted from the phase locked loop 30.
The phase locked loop 30 receives an input clock signal CLKIN and generates 7-phase clock signals for respectively sampling the input parallel data signals.
FIG. 2 is a circuit diagram illustrating transmission between a LVDS driver and a LVDS receiver. In FIG. 2, only the first LVDS driver 41 among the LVDS drivers 41, 42, 43 and 44 is illustrated for brevity.
Referring to FIG. 2, the LVDS driver 41 includes a constant current source AD that provides 3.5 mA of current and four transistor switches M1, M2, M3 and M4. The switches M1, M2, M3 and M4 is turned on/off in response to logic data signals input to the switches, namely, a serial data signal DA, and thus causing a current to flow through a transmission line. Therefore, the LVDS driver 41 generates a voltage difference of +/−350 mV level across a resistor Rx of 100 ohms-coupled to input terminals of a LVDS receiver 50. The LVDS receiver 50 amplifies the input voltage difference of +/−350 mV and converts the amplified voltage difference into a logic level, and thus determines whether the converted logic level corresponds to a logic high or a logic low level.
FIG. 3 is a timing diagram illustrating a process of converting a logic data signal input to the LVDS driver illustrated in FIG. 2 into a low voltage differential signal.
Referring to FIG. 2 and FIG. 3, when the serial data signal (DA) (i.e., the logic data) is input, a current of +3.5 mA/−3.5 mA flows in the transmission line depending on the high/low state. When the voltage across the resistor Rx coupled to the input terminals of the LVDS receiver 50 corresponds to a logic high level, the voltage of +350 mV is generated across the resistor Rx. When the voltage across the resistor Rx corresponds to a logic low level, the voltage of −350 mV is generated across the resistor Rx.
However, when the data signal is transmitted at a relatively slow rate, a voltage difference, generally of +/−350 mV level is generated at input terminals of a LVDS receiver. However, the voltage difference is decreased as the transmission speed of the data signals is increased.
For example, assuming that an input data signal is input at a speed of 135 MHz, the signaling driver should be operated at a data rate of 945 Mbps (=135×7) since the LVDS driver needs to process the 7 signals. However, since the constant current source AD continuously generates a current of 3.5 mA, the output signal is increasingly attenuated as the data rate is increased, and thus the amplitude is decreased.
In addition, the output signal is influenced by the length of the connected transmission line and by the load condition between the LVDS driver and the LVDS receiver.
Accordingly, the attenuation of the output signal deteriorates an Eye characteristic of the data signal and prevents normal data from being transmitted to the LVDS receiver.
As such, a pre-emphasis technique of generating a pre-emphasis pulse signal by detecting a transition section of the transmitted data signal and then compensating for amplitude of the data signal according to the pre-emphasis pulse signal has been employed.
FIG. 4 is a conceptual diagram illustrating a conventional pre-emphasis technique.
Referring to FIG. 4, the Eye characteristic is improved by compensating for a distortion using a pre-emphasis approach that compensates for (or reinforces) the amplitude during the transition section of the signal, when the low voltage differential signal is transmitted.
FIG. 5 is a schematic circuit diagram illustrating a configuration of a conventional pre-emphasis pulse signal generation circuit.
Referring to FIG. 5, the conventional pre-emphasis pulse signal generation circuit delays the input serial data signal (DA) using a delay unit 60 composed of a plurality of serially connected inverters 61 for a predetermined time. The delayed serial data signal (DA′) and the serial data signal (DA) are provided to an exclusive-OR gate (XOR gate) 70, and a pre-emphasis pulse signal (PEM) for designating an amplitude reinforcement location is generated.
FIG. 6 is a timing diagram illustrating the primary signals for the pre-emphasis pulse signal generation circuit shown in FIG. 5.
Referring to FIG. 6, the pre-emphasis pulse signal (PEM) is generated for 1 unit interval (UI) during the transition sections, which require the pre-emphasis, of the serial data signal (DA), based on the results of an XOR operation on the input serial data signal (DA) and the delayed serial data signal (DA′).
As described above, the conventional pre-emphasis depends on a delay time due to delay cells such as an inverter. However, such delay time is very sensitive to environmental factors such as process, voltage and temperature (PVT) (i.e., a process change), an operating power voltage change and an operating temperature change.
Accordingly, since the pre-emphasis pulse signal generated by the conventional pre-emphasis pulse signal generation circuit is readily varied by environmental factors and is not regularly maintained due to the characteristics of the delay circuit, it is difficult to perform accurate pre-emphasis, in particular with increasing data transmission rates.